# Analog IC Design Errata

Below is a listing of known errors in the first printing of Analog Integrated Circuit Design, 2nd edition.

### 97 thoughts on “Analog IC Design Errata”

1. Hello Professor,

On page 492, eq. 12.90, a factor of 2 is missing? Currently, the equation is not consistent with eq. 12.89.

Thanks!

• Thanks – I have added this to the errata above. Note this also affects Example 12.7 on the same page.

2. Sect. 9.4.4, page 397, equation 9.122:
I believe the algebra is such that the second term should be 16/9, not 4/9, after setting Cgs = Cin from equ. 9.121.

Thanks, great book.

• Yes – thanks for the correction. I’ve included it in the list above.

3. Pg. 190, Eq. 4.203, Sec. 4.4

Shouldn’t we have Gin(Cgs1 + Cs) instead of Gin(Cs) in denominator for expression for Q?

• Thanks for this. I have added it to the Errata above. Note that the final approximation in equation (4.204) is still valid.

4. on page 244, equation 6.1 says:

Av1 = -gm1(rds2||d*rds4)

where it should just say:

Av1 = -gm1(rds2||rds4)

In other words, there’s a minor typo which adds in a ‘d’ next to rds4 that should not be there.

• Thanks for reporting this. I’ve added it to the errata.

5. There is one sentence in page 130 which does not make sense. Whoever was the author of this sentence is grossly incompetent in English. There are many many other mistakes but this mistake is very severe since this disrupts understanding of a very important part

“Since the smallest output voltage,VD4
, can be without Q4 entering the triode region is given by Vds2+Veff , the minimum allowed voltage for Vout is give by”

• Thanks for catching this. It should read, “…Since the smallest the output voltage, VD4, can be…” This now appears in the errata above. We’d be happy to hear about the other mistakes you’ve noticed.

6. figure 1.30(a) on page 46 (second edition): the current Id seems unusually large versus Vgs… should the unit for Id be mA rather than A? If using this plot, by plugging in theta = 1.7V^-1, Vgs = 1V, Id = 0.3A, Vth = 0.45V (gives muCox(W/L)=2.72mA/V^2), one will get m = -0.106 by using equation 1.126. But if changing Id = 0.3A->0.3mA, one will arrive m = 2 that is more reasonable.

• Yes, you are correct – the units of ID in Figure 1.30(a) should be mA. This now appears in the Errata. Thanks.

7. P.764, example 19.15
equation of fj(t):

Should the denominator of the power of e be 5*10^(-23) instead of 5*10^(-25)?

Thanks

• Yes – good catch! I have updated the errata accordingly. Thank you.

8. P.764, the equation fj(t) in Example 19.15:

Should the power of e be 5*10^(-23) instead of 5*10^(-25)?

• Yes – this has already been reflected in the errata above. Thanks!

9. hi there,

(4.175) is Cout=Cgd2+Cdb2+CL+Cbias=20pF+25fF+7pF+25pF=52.025pF

(4.175) should be Cout=Cgd2+Cdb2+CL+Cbias=20fF+25fF+7pF+25pF=32.045pF

br,

mario

• I believe you are using some of the wrong values. The sum is Cout = 15fF + 20fF + 5pF + 20fF = 5.055 pF, which is the correct value given in equation (4.175).

10. Page 281, third line:
The only difference [between] them is…

• Oops – thanks for the correction. Much appreciated.

11. Dear professor,

About the problem 10.4 on page 442. The problem can be solved and that is clear for me. However, if the input signal Vin can be only positive value because supply voltages are gnd and 5V so can the comparator output go to high? So do we have the think that the input Vin is just relative signal like positive or negative?

Best regards,

Jan

• The comparator compares the input voltage to the threshold of the inverter, VDD/2. It produces either a high (5 V) or low (0 V) logic level depending on (Vin – VDD/2).

12. Page670,the comparator offset should less than Vref/8, but the book in first paragraph is less than Vref/4

• Yes, thanks for noticing this. It’s been added to the errata.

13. Page 111 and Fig. 2.36
Why not connecting the metal shield to VDD?
Last three lines in 2nd paragraph mention that the nwell acts as a bypass cap. This is true if the shield is VDD rather than GND.
Also in this sentence VDD should probably be replaced by GND: “this helps minimize noise in the substrate, which is connected to VDD”

• Yes, this paragraph is jumping around, mixing up a few different possibilities. The intention is to connect such shields to a dc voltage via a very low impedance (i.e. a small-signal ground). This may be either VDD or ground. Generally, ground has the lowest impedance. Moreover, if a dedicated shielding ground is used, as suggested in the text, it should have less noise on it. However, if VDD is used, you may get the benefit of additional bypass capacitance. Finally, of course, a p-type substrate as pictured in Figure 2.36 would normally be connected to ground, as you said. Thanks for your comment!

14. In p.250 exp6.4, For a 10-mv step, the slope by (6.23) is 0.05 V/us, not 0.05 V/s.

• Thank you – this is now included in the errata above.

15. I have one question about a circuit proposed several times in the book in Fig. 14.34, Fig. 14.35, Fig. 14.36, and Fig. 16.12. In this circuit there is no DC path for the inverting terminal of the op-amp. This node is always floating, and it is not set by any of the switches. I would appreciate if you can let me know how you set the DC bias at this point.

• Capacitor C3 in Fig. 14.34 is alternately switched between ground and the inverting input terminal of the op amp. Over several clock cycles, this provides a path for charge to flow to or from the inverting input terminal, allowing its voltage to settle to an appropriate value.

16. chapter 7, fig15. (Banba Bandgap reference)

to make valid eq(7.57)
resistor Ra in the right side should be Ra/M
and I2a_right = I2a_left/M.

• Actually, the leftmost resistor should be Ra/M, as indicated in the errata above.

17. Page 732: second key point: “LSB2” => “2” should be superscript.

• Got it – thank you!

18. Page 711: typo in “often an desirable trade-off in integrated circuits”. “an” should be “a”.

19. Page 708, there is a typo in the key point: 1.5 bit/octave should be 2.5 bit/octave

• Thanks – added this to the errata.

20. There is an error in the errata for the correction of page 249. This correction is for wz not wp2.

• Thank you. This has been corrected.

21. Section 18.3.1 (p.710) specifies fs=5.6448 MHz and f0=44.1 kHz to give an OSR=128. But per the definition of OSR used in the book (eq. 18.8), this should give an OSR=fs/(2*f0)=64. I assume the intention here might be to say 2*f0=44.1 kHz ?

• Yes you are correct – thanks for the comment. I will add it to the errata.

22. Hi, in eqn 6.43, zero is on the left-half plane if Rc=0. It has to be on the RHP. Actually, if you look at the sentence below also, it mentions that if Rc is too large, zero will move from RHP to LHP. It think there is an extra (-) sign in that eqn.

• No. The convention used throughout that section of the book, and in most analog circuit analysis, is that when a pole (or zero) frequency is positive, it refers to a left-half plane pole (or zero). See, for example, equations (6.19), (6.20), and (6.21) all of which are positive describing left-half plane poles and zeros. Thus, the negative value of (6.43) when Rc=0 implies a right-half plane zero, as expected.

23. Section 7.3.3, Fig. 7.15, and Eq. (7.57):
The parameter “N” is not defined in the text.

• Yes, this parameter is not explicitly defined. It is hopefully obvious to the reader that “N” refers to the number of diodes in parallel.

24. There is an error in the errata. For the correction of the mistake in page 320 regarding opamp polarity, it is mentioned that the ref figure is “none”. The ref figure is Fig. 7.15. Please correct.

• Fixed – thanks!

25. Page 314, Section 7.3.2:
“both transistors have the same collector currents and collector-emitter voltages”
Should be “and collector-base voltages”.

• Agreed – I have added this to the errata.

26. Section 7.2.1, page 309, 2nd paragraph:
1) The reduction in mobility is 28%, not 27%.
2) If the mobility decreases by 28%, then Veff should be: Veff/0.72 = 1.39Veff –> Veff should increase by 39%, not 27%.

• 1) My calculation gave 0.2786 – a minor point!
2) Agreed – Veff should increase by 39%, not 27%. I have added this to the errata – thanks!

27. Example 7.1-b)
ID is in inverse proportion to R.
BUT Veff is proportional to sqrt of ID rather than ID.
Thus, “0.9” should be replaced by “sqrt(0.9)”.
The correct answer should be 717mV

• Yes – thank you! I’ve put this on the errata.

28. In Section 7.2.2, second paragraph, third line, TWO occurrences:
Q13 should be replaced by Q14.

• Right. The current density of Q14 is five times greater than that of Q4. Hence, the gate voltage of Q14 is suitable for use as the PMOS cascode bias Vcasc-p. Added to the errata – thank you!

29. page 420,Example 10.3, solution part:second line,”using (10.8),this …=-2.8mV”,i think it is “-28mV”,dose it mean: 2Vx1.4fF/101.4fF=2.8mV ?

• Yes – you are correct. The charge injection due to overlap capacitance should be 27.6mV and so the total charge is found by adding 27.6mV and 52.7mV for a total of 80mV. I have added this to the errata.

30. On page 24(second ed.), you state that for a p-channel MOS to conduct, it must have VSG>Vtp, where Vtp is a negative quantity. So as a consequence, VSG=0 gives a conducting transistor since 0 is greater than any negative number, but this cannot be true ??

• It is easy to get the signs confused in this context. Without having to get into the weeds of it myself, it is clear that your understanding of the matter is correct!

• I don’t see why this hasn’t been added to the errata. It is an obvious mistake and it seems silly to have to find it in the comments.

• This is not included in the errata because, strictly speaking, the text is correct. For example, consider equation replacing VGS with VSG and Vtn> with -Vtp, as indicated in the text. The final term of (1.63) becomes (VSG + Vtp). Since Vtp is a negative quantity and the square law is only valid when the bracketed term is greater than zero, we must have VSG > |Vtp| for the transistor to be “on” with current flowing, as we expect.

However, I understand that all these minus signs can be confusing and I just wanted to assure Anders that I believe his basic understanding is correct.

31. Dear Professors,

The equations 5.2 and 5.3 in Chapter 5 should have a negative sign for the loop-gain term. If we set input to zero for loop-gain calculations, and follow the loop in Fig.5.1, v=-ABx and L=-AB, due to terminal v multiplying with -1. This also implies that there is a negative feedback. These equations should be included in the list of errata.

This book is one of my favorites and I liked this time in 2nd edition, topic of feedback was given more attention.

Thanks

• The book adopts the more common convention of defining the loop gain of a negative feedback amplifier as positive (at low frequency). The signal x experiences gains of A and then B to the point V so the gain from X to V is AB not -AB. If one defines L=-AB, then all the equations of 5.4 and onward must also be modified.
V=ABX=AB(U-V) so V=U.AB/(1+AB) & Y=A(U-V) so Y=U.A/(1+AB)

32. In the solution of Example 5.1 on page 206 the change in the closed-loop gain should be less than 5%, because |4.9751-4.9975|=0.0224, which is 2.24% change.

• The change in gain is expressed as a percentage of the originally computed gain. Hence,
|4.9751-4.9975|/4.9975 * 100 = 0.00448*100 = 0.45%

33. I believe 4.133 is incorrect. It should be
wp2 = 1/(RS*(Cgs1+Cgd1))

4.133 is derived assuming C2 is large directly on 4.127,
However we cannot not use 4.127 directly (4.127 is based on the assumption that Cdg1*gm1*R2 >> R2*C2 which is in contradiction with the case we are considering in 4.132.

• There is no contradiction in the most common cases.

The assumption of widely-spaced real poles which leads to (4.126) & (4.127) is tantamount to assuming the Miller capacitance, Cgd1*gm1*R2 >> C2. This is reasonable in the common case where Cgd1 includes a compensation capacitor Cc so that the Miller effect makes it much larger than C2.

Then, in order to arrive at (4.133) from (4.127), we assume C2 >> Cgs1, also reasonable assuming the opamp is loaded by a capacitance much bigger than Cgs1. This then allows us to neglect the term Cgs1*Cgd1 in the denominator of (4.128) as being much smaller than C2*Cgd1.

34. Looking at equation 1.90 and example 1.13，I find Cov having different definitions.

• Yes – you are correct. Example 1.13 should more properly refer to Cov‘, the overlap capacitance normalized per unit length of gate width. Hence, Cov = Cov‘ W. Thanks for catching this!

35. In EXAMPLE 1.16,I have a question about the definition of Ioff. Only when VGS=0,we have Ioff. Then Ioff has nothing to do with the changes of VGS,and it is a function of vth. Is that Right,Dr Carusone?

• Yes – your interpretation is consistent with equation (1.121). This definition is particularly suitable for CMOS digital logic circuits where the MOSFETs act as switches that are OFF when VGS = 0. In analog circuits, sometimes the source (and even the body terminal) may not be at ground. It may be possible to reduce subthreshold leakage in these cases by decreasing VGS even further, below zero. Thanks for raising this confusing point!

36. The second pole and zero frequency is incorrect in example 4.7 on page 159-163. The circuit shows 1pF, but the calculations must have used 100pF, because the frequency is off by 100.

• Thanks very much for catching this. It’s now reflected in the errata.

37. On page 182,Equation4.168 Rout is rds2//RL.I think Rout is gm2rds2rds1//RL;
Equation4.170,gs2=1/rs2=gin2+gds1,gin2 I think is gm2;
Equation4.171 I think gin2 is gm2 too.

• Equation (4.168) refers to rd2 which is the small-signal resistance seen looking into the drain of Q2, not simply rds2 as you suggest. The substitution for rd2 is then made in (4.174). In equations (4.170) and (4.171), note that gin2 is approximately gm2, but is more accurately given by the expression in (4.160) which takes into account the circuit’s finite load impedance.

38. Page 124, last paragraph, first sentence:
“…, the input impedance, rout, is found to be 1/gm…” -> rout should be rin.

39. Equation 6.71, page 261. It says Veff7 / Veff16 = …
I assume it should be Veff7 / Veff6? (since there’s not even a Q16).

• No, not quite, although of course there is a typo there. In fact, in equation (6.71) Veff16 should be replaced by Veff9, the triode device realizing Rc. Thanks.

40. On page 420, example 10.3.
There’s a print error on Vdd=1V which should be 2V according to the solution below.

41. Equation 1.146: I think there should be Dp instead of Dn

42. Page 197 Figure 4.37: Dependent current source arrow direction should be up in order to model + gain of the active load diff. pair.

43. Page 196 Fig. 4.35 right-hand side dependent current source arrow should be upwards since vgs2=-vg1/2. Then page 195 Eqn. 4.226 becomes positive.

44. Figure 7.13 – Based on Ye’s Paper, the terminals of OP-AMP are incorrectly connected. Should they not be reversed.

• Yes – for Fig. 7.13(b) only they should be reversed in order to provide negative feedback, and in accordance with Ye’s paper. Fig. 7.13(a) is correct as is. Thanks!

45. Page 510, Ex. 12.10, Fig. 12.41(b): Output differential voltage polarization should be reversed in order to have a negative gain of (-1/(sRC)) as stated in the solution.

46. Page 225 example 4.9 solution:
Fig. 5.13b: simplified small-signal model of the diff pair’s dependent current source direction should be reversed (Av=+gm*Rout).
Then Fig. 5.13c becomes correct for dependent current source:
gm1(Vin-Vout)”up arrow”
= gm1(0-Vt) “up arrow”
=-gm1*Vt “up arrow”
= gm1*Vt “down arrow”

47. Page 170 example 4.8 solution:

In the first sentence, Miller feedback admittance is stated as “Y(s)=1/sC”,which should be Y(s)=sC.

48. polarity of opamp on fig 7.15 is wrong!!!

49. on page 446 says Since this charge is negative, it will cause the junction voltages to have negative glitches.
i think positive charge is right since switch of Fig.11.3 is PMOS transistor.

• I think you are confused by the symbol in Fig. 11.3. In that figure, Q1 is in fact an NMOS transistor, as indicated by the arrowhead.

50. In p.145 sec. 4.1 last sentence in last paragraph.
“Further, the real parts of all the poles will be positive for stable transfer functions.”
The term “positive” should be modified as “negative”!

51. I noticed that on page 148 that with f=10Hz, ω = 2πf = 62.83 rad/s and not 628.3 rad/s

52. The caption on Fig 4.1 on page 151 says lowpass circuit but the circuit is a highpass.

• In fact, the transfer function for Vin/Vout of that circuit is, indeed, lowpass. You may find the analysis in Example 4.3.

• The H(s) in the Ex. 4.3 is a high-pass filter, sRC/(1+sRC). Which part of the example shows a low-pass transfer function? I got a little confused by this. The basic formula looks like low-pass, but as the circuit transfer function derives, it is clear a high-pass filter, doesn’t it? Thank you.