<?xml version="1.0" encoding="UTF-8"?>
<?xml-stylesheet type="text/xsl" href="https://analogicdesign.com/wp-sitemap.xsl" ?>
<urlset xmlns="http://www.sitemaps.org/schemas/sitemap/0.9"><url><loc>https://analogicdesign.com/</loc><lastmod>2020-12-19T03:39:05+00:00</lastmod></url><url><loc>https://analogicdesign.com/about/aicd/</loc><lastmod>2020-12-18T15:12:10+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/</loc><lastmod>2020-12-18T15:36:53+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/</loc><lastmod>2021-02-05T03:05:12+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/labs/</loc><lastmod>2025-09-05T11:09:34+00:00</lastmod></url><url><loc>https://analogicdesign.com/for-instructors/</loc><lastmod>2021-02-05T14:17:40+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/errata/</loc><lastmod>2026-05-27T08:47:43+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/</loc><lastmod>2012-08-10T20:34:54+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/</loc><lastmod>2012-08-10T20:37:28+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/problem-1-4/</loc><lastmod>2012-08-10T02:20:21+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/example-1-6/</loc><lastmod>2012-08-10T01:17:52+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-2-netlists/</loc><lastmod>2012-08-10T20:37:45+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-4-netlists/</loc><lastmod>2011-12-25T01:00:45+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-6-netlists/</loc><lastmod>2011-12-25T03:52:54+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-7-netlists/</loc><lastmod>2011-12-25T04:19:06+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-10-netlists/</loc><lastmod>2012-01-20T05:49:33+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-14-netlists/</loc><lastmod>2012-01-20T05:50:03+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/problem-1-27/</loc><lastmod>2011-12-25T05:10:22+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-2-netlists/problem-2-14/</loc><lastmod>2020-12-09T14:14:02+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-2-netlists/example-2-3/</loc><lastmod>2012-09-20T17:54:00+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/example-3-1/</loc><lastmod>2012-09-24T04:33:58+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/example-3-2/</loc><lastmod>2012-09-30T03:49:08+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/problem-3-2/</loc><lastmod>2012-09-24T04:34:22+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/problem-3-3/</loc><lastmod>2012-09-28T22:34:14+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/problem-3-9/</loc><lastmod>2012-09-30T03:46:51+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/problem-3-16/</loc><lastmod>2012-09-30T03:42:44+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-3-netlists/problem-3-29/</loc><lastmod>2012-09-30T03:06:25+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-4-netlists/example-4-11/</loc><lastmod>2012-09-30T04:39:08+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-4-netlists/example-4-12/</loc><lastmod>2012-09-30T04:41:36+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-4-netlists/problem-4-12/</loc><lastmod>2012-10-02T02:37:07+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-4-netlists/problem-4-13/</loc><lastmod>2012-09-30T21:07:05+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-4-netlists/problem-4-14/</loc><lastmod>2012-10-01T05:20:33+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-4-netlists/problem-4-25/</loc><lastmod>2012-10-01T03:52:45+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-6-netlists/example-6-1/</loc><lastmod>2012-11-12T21:42:28+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-6-netlists/example-6-9/</loc><lastmod>2012-10-16T02:55:05+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-6-netlists/example-6-11/</loc><lastmod>2012-10-12T14:30:36+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-7-netlists/fig-7-8/</loc><lastmod>2012-10-20T00:08:09+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-7-netlists/problem-7-1/</loc><lastmod>2012-10-19T04:20:06+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-10-netlists/problem-10-10/</loc><lastmod>2012-10-29T03:56:46+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-14-netlists/problem-14-2/</loc><lastmod>2012-10-30T01:55:06+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-14-netlists/problem-14-3/</loc><lastmod>2012-10-30T02:15:14+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-14-netlists/problem-14-20/</loc><lastmod>2012-11-01T03:31:38+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-14-netlists/problem-14-21/</loc><lastmod>2012-11-01T04:29:55+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/problem-1-27/0-8um-cmos-process/</loc><lastmod>2012-09-16T23:00:15+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/problem-1-27/0-35um-cmos-process/</loc><lastmod>2012-09-07T20:18:57+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/problem-1-27/0-18um-cmos-process/</loc><lastmod>2012-09-14T18:07:53+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-1-netlists/problem-1-27/45nm-cmos-process/</loc><lastmod>2012-09-17T04:19:04+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-8-netlists/</loc><lastmod>2012-01-20T05:49:08+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/chapter-8-netlists/problem-8-3/</loc><lastmod>2012-10-25T04:44:35+00:00</lastmod></url><url><loc>https://analogicdesign.com/more/</loc><lastmod>2020-12-18T15:11:27+00:00</lastmod></url><url><loc>https://analogicdesign.com/more/about-the-authors/</loc><lastmod>2024-10-28T14:52:43+00:00</lastmod></url><url><loc>https://analogicdesign.com/more/read-more/</loc><lastmod>2020-12-18T15:09:03+00:00</lastmod></url><url><loc>https://analogicdesign.com/more/training-services/</loc><lastmod>2020-12-18T16:08:20+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/netlists-models/model-files/</loc><lastmod>2021-08-28T12:58:46+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/videos/</loc><lastmod>2023-08-23T15:15:39+00:00</lastmod></url><url><loc>https://analogicdesign.com/about/microelectronic-circuits-table-of-contents/</loc><lastmod>2020-12-18T15:49:21+00:00</lastmod></url><url><loc>https://analogicdesign.com/students/microelectronic-circuits-errata/</loc><lastmod>2021-02-10T22:16:31+00:00</lastmod></url><url><loc>https://analogicdesign.com/for-instructors/microelectronic-circuits-solution-manual-errata/</loc><lastmod>2021-11-03T20:21:48+00:00</lastmod></url><url><loc>https://analogicdesign.com/more/training-services/analog-ic-design-in-nanoscale-cmos-short-course/</loc><lastmod>2022-02-10T03:28:50+00:00</lastmod></url></urlset>
