Analog Integrated Circuit Design

2nd edition


Problem 2.14

1. Schematic

2. HSPICE Netlist

* Problem 2.14

 

* MOS model

.include p18_cmos_models_tt.inc

 

* main circuit

mn1 1 2 0 0 nmos L=0.2u W=20u

 

* voltage source

vdd 1 0 1.8

vgs 2 0 dc 0.613 ac 1

** vgs dc value adjusted to ensure Id is 0.5mA

 

* analysis

.op

.ac dec 100 1k 100G

 

* options

.options post

 

*slow version

.alter

.include p18_cmos_models_ss.inc

.param vt_shift = 0

vgs 2 0 dc 0.624 ac 1

** vgs dc value adjusted to ensure Id is 0.5mA
.end

3. Simulation Result

 

Variation fT [GHz] ΔId [%]
Typical 18.7 0
VCox: -5%
µn: -10%
17.8 -4.8



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