About The Author

About the Author

Tony Chan Carusone received his Ph.D. from the University of Toronto in 2002 and has since been a professor with the Department of Electrical and Computer Engineering at the University of Toronto.  He is also an occasional consultant to industry in the areas of integrated circuit design and digital communication.

He and his graduate students have received seven best-paper awards at leading conferences for their work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017, and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters.  He was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and currently serves on the Technical Program Committee of the International Solid-State Circuits Conference.

Find out more about Tony and his research at the Integrated Systems Laboratory at the University of Toronto.

6 thoughts on “About The Author”

  1. Hi,
    My professor is using one of the file here for an LTSpice assignment that is worth 40% of my final mark.

    I need help adding 0.35 um CMOS file to LTSpice to use and simulate with. Any advice how to import?
    I have tried adding to the directory but I have an error. I also tried the spice directive .op, but I don’t understand why there are three files _ss, _ff and _tt …etc.

  2. Hi,
    In chapter 6 (Basic Op-Amp Design and Compensation) on Page no. 252, you say slew-rate(SR) can be increased by increasing Veff.
    But increasing Veff by some ratio, also decreases unity gain frequency(Wta) by same ratio, making SR independent of Veff.
    Since SR = Veff*Wta.

    Can you clarify, Please.

    • The key point is the assumption that the two-stage opamp is “properly compensated” as it says near the bottom of page 252. As you say, increasing Veff with constant bias current reduces the unity-gain frequency. Therefore, the compensation capacitor size can also be reduced while maintaining the same phase margin. This reduction in Cc provides an attendant improvement in slew rate.

  3. Hi,Professors. Recently I am read the great book ” Analog integrated circuit design 2nd”, but I have a question about the sentence below( in page 180 of chapter4)

    “This assumes rin<= or >>Rs, could you help me please.

    • Assuming rin << Rs means that Rs may be neglected in (4.162> and the time constant is approximately rinCgs. Then, a further assumption is made that rin is approximately 1/gm to arrive at the final expression in (4.162).


Leave a Comment