Analog Integrated Circuit Design

2nd edition


Problem 3.9

1. Schematic

2. HSPICE Netlist

* Problem 3.9

 

* MOS model

.include p35_cmos_models_tt.inc

 

* main circuit

mn1 3 4 0 0 nmos L=0.8u W=20u

mp2 3 2 1 1 pmos L=0.8u W=20u

mp3 2 2 1 1 pmos L=0.8u W=20u

 

* current source

id 2 0 dc 100u

 

* voltage source

Vdd 1 0 dc 3.3

vin 4 0 dc 0.782 ac 1

** vin dc value adjusted to ensure mn1 is in active mode

 

* analysis

.op

.ac dec 10 1k 100G

 

* options

.options post

.end

3. Simulation Result

 

Variation AV [V/V] Veff [mV] Ids1 [µA]
W/L = 10um/0.4µm  (Example 3.2) 22.1 222 100.8
W/L = 20um/0.8µm  (Problem 3.9) 57.4 231 100.4



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