Analog Integrated Circuit Design

2nd edition


Example 4.11

1. Schematic

2. HSPICE Netlist

* Example 4.11

 

* MOS model

.include p18_cmos_models_tt.inc

 

* main circuit

mn1 3 4 0 0 nmos L=0.24u W=10u

mp2 3 2 1 1 pmos L=0.72u W=30u

mp3 2 2 1 1 pmos L=0.72u W=3u

cl 3 0 100f

rs 4 5 40k

 

* current source

id 2 0 dc 50u

 

* voltage source

Vdd 1 0 dc 1.8

vin 5 0 dc 0.774 ac 1

** vin dc value adjusted to ensure mn1 is in active mode

 

* analysis

.op

.ac dec 10 1k 1G

 

* options

.options post

.end

3. Simulation Result

 

AV [V/V] P [mW] ω-3dB [MHz]
Specifications 20 1 maximum
Simulation results 25.4  0.99  11.6



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