Analog Integrated Circuit Design

2nd edition


Problem 4.14

1. Schematic

2. HSPICE Netlist

2-a. 0.18-µm CMOS process

* Problem 4.14 a. 0.18um process

 

* MOS model

.include p18_cmos_models_tt.inc

 

* main circuit

mp1 1 2 3 3 pmos L=0.18u W=531u

cl 1 0 25p

 

* current source

id 1 0 dc 0.8m

 

* voltage source

vdd 3 0 dc 1.8

vin 3 2 dc 0.55 ac 1

** vin dc value adjusted to ensure mp1 is in strong inversion

 

* analysis

.op

.ac dec 10 1k 100G

 

* options

.options post

.end

2-b. 45-nm CMOS process

* Problem 4.14 b. 45um process

 

* MOS model

.include p045_cmos_models_tt.inc

 

* main circuit

mp1 1 2 3 3 pmos L=45n W=112u

cl 1 0 25p

 

* current source

id 1 0 dc 0.8m

 

* voltage source

vdd 3 0 dc 1.8

vin 3 2 dc 0.55 ac 1

** vin dc value adjusted to ensure mp1 is in strong inversion

 

* analysis

.op

.ac dec 10 1k 100G

 

* options

.options post

.end

3. Simulation Result

 

fta [MHz]
0.18µm CMOS process 93
45nm CMOS process 72



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