Analog IC Design Errata

Analog Integrated Circuit Design, 2nd Edition Errata

Below is a listing of known errors in the first printing of Analog Integrated Circuit Design, 2nd edition.

Page No. Section Example/ Problem Figure Equation reference Original Correction
23 1.2.3 1.8 none none Using (1.67), we
find for Vds = Veff
= 0.4V,
Using (1.67), we
find for Vds = Veff
= 0.35V,
23 1.2.3 1.8 none none In the case where VDS = Veff + 0.5V = 0.9V, we have In the case where VDS = Veff + 0.5V = 0.85V, we have
33 1.2.7 1.13 none none Cov = 2.0 x 10-4 pF/μm Cov‘ = 2.0 x 10-4 pF/μm
46 1.4.2 none 1.30(a) none The units of ID are mistakenly labeled (A) The units of ID should be (mA)
47 1.4.3 none 1.31 none In the plot of ID
vs. VGS, the slope of ID vs. VGS in mobility degradation looks same as or
larger than that of square law, which contradicts the plot of gm vs. VGS
Eliminate curvature
on ID vs VGS
plot in mobility degradation.
53 1.5.3 none 1.33 none Two text labels
include the “section end” character
Replace with
“/”
62 1.7.1 none none 1.146 Dn Dp
70 1.10.2 P1.12 none none The technology node
and the values of Vdb, Vsb,
and Cj-sw are not given
Assume the 0.35μm CMOS technology, Vdb
= Vsb = 0, and ignore sidewall
capacitances.
101 2.3.3 none none none gm/ID = 1/(2Veff) gm/ID = 2/Veff
102 2.3.3 none none 2.19 σ2(ΔVGS) = 1/WL[AVt02(gm/ID)2 + AK’2] σ2(ΔVGS) = 1/WL[AVt02 + (ID/gm)2AK’2]
106 2.4.2 2.6 2.31 none left and right sides
of the figure have been cropped
left and right
layout labels should indicate 10μm and 19.6μm dimensions
respectively
111 2.4.4 none none none The text describing the n-well shield (Fig. 2.36) is confusing The shield may be connected to either VDD or a dedicated ground, offering different advantages in either case
124 3.4 none none none …, the input impedance, rout, is found to be 1/gm …, the input impedance, rin, is found to be 1/gm
130 3.6 none none none …Since the smallest output voltage, VD4, can be… …Since the smallest the output voltage, VD4, can be…
140 3.11.2 P3.12 none none … shown
in Fig. P3.11.
… shown
in Fig. P3.12.
145 4.1 none none none Further, the real parts of all the poles will be positive… Further, the real parts of all the poles will be negative…
148 4.1.2 4.2 none none … for the case f = 10 Hz, where ω = 2πf = 628.3 rad, … … for the case f = 10 Hz, where ω = 2πf = 62.83 rad, …
154 4.1.2 4.5 none 4.60 ∠A(ω) = -tan(ω/ω-3dB)-1 ∠A(ω) = -tan-1(ω/ω-3dB)
155 4.1.3 none none 4.70 Φ = -tan-1(ω/ωp1) – tan(ω/ωp2) Φ = -tan-1(ω/ωp1) – tan-1
(ω/ωp2)
161 4.1.4 4.7 none 4.93 1.05 x 108 rad/sec 1.05 x 1010 rad/sec
161 4.1.4 4.7 none 4.94 5 x 106 rad/sec 5 x 108 rad/sec
170 4.2.3 4.8 none none … to the case where Y(s) = 1/sC. … to the case where Y(s) = sC.
175 4.2.4 4.9 4.19 none   gm1
labels should be beside the dependent current sources
176 4.2.4 4.10 none none use the transistor parameters listed in Table 1.5
for the 0.8-μm CMOS technology in
Table 1.5.
use the transistor parameters listed in Table 1.5
for the 0.8-μm CMOS technology.
176 4.2.4 4.10 none 4.158 the denominator of
equation (4.152):Rin[Cgs1 + Cgs1(1
+ gm1R2)] + R2(Cgd1 + C2)
the denominator of
equation (4.152):Rs[Cgs1 + Cgs1(1 +
gm1R2)] + R2(Cgd1 + C2)
177 4.2.5 4.11 4.13 none L1=|Ao| l L1 Veff,1 L1=(|Ao| l L1 Veff,1) / 2
179 4.2.5 4.12 none none 2 x 355mA x 0.18μm / (270mA/V2 x
(0.1V)2)
2 x 350mA x 0.18μm / (270mA/V2 x
(0.1V)2)
190 4.4 none none 4.203 &
4.204
denominator term: GinCs Gin(Cgs1 + Cs); the final approximation in (4.204) is still valid
191 4.4 4.16 none 4.212 = (4.27 x 109
rad/s = 2π x 680 MHz)
= 4.27 x 109
rad/s = 2π x 680 MHz
194 4.5.1 none 4.31 none capacitor symbol overlaps
the label, Cdb
move capacitor
symbol to the left
195 4.5.3 none none 4.226 negative sign in the numerator no negative sign in the numerator
196 4.5.3 none 4.34(a) none label “Vout” is mislocated move “Vout” label to the output below “RD
196 5.4.3 none 4.35 none dependent current source on the right points down dependent current source on the right points up
197 5.4.3 none 4.36 none dependent current source on the right points down dependent current source on the right points up
197 5.4.3 none 4.37 none dependent current source on the right points down dependent current source on the right points up
205 5.1.2 none none 5.7 ΔA / [(1+L)2+ ΔAβ] ΔA / [(1+L)2 + ΔAβ(1+L)]
209 5.2 5.3 none none In practice, the voltage at v will increase above vin In practice, the voltage at v+ will increase above vin
210 5.2.1 none none none Key Point: “…
-180 degres …”
Key Point: “…
-180 degrees …”
215 5.3.1 none none 5.29 Second equals sign:
“=”
Second equals sign
should be approximately equals
216 5.3.1 5.6 5.9(b) none expression in the
figure: “s/ωta
expression in the
figure: ” ωta/s”
217 5.3.1 5.6 none none … is well approximated by s/ωta. … is well approximated by ωta/s.
217 5.3.1 5.6 none 5.32 first term on right
side: “(s/ ωta)”
first term on right
side: “(ωta /s)”
221 5.4 none none none Key Point: “…
desired gain, β …”
Key Point: “…
desired gain, 1/ β …”
225 5.4.1 5.9 5.13(b) none arrow points down on the dependent source gm,1 arrow points up on the dependent source gm,1
225 5.4.1 5.9 5.13(c) none line connecting the tops of Zx and Cgs,5 is broken line connecting the tops of Zx and Cgs,5 should be connected
225 5.4.1 5.9 5.13(c) none Cgs,1/2 Cgs,1 /2
229 5.4.2 5.11 none none 2π 2.86MHz 2π 28.6MHz
235 5.5 none none none Key Point: “…
-180 degres …”
Key Point: “…
-180 degrees …”
235 5.5 none none none Key Point: “…
desired gain, β…”
Key Point: “…
desired gain, 1/β …”
244 6.1.1 none none 6.1 (rds2||drds4) (rds2||rds4)
244 6.1.1 6.1 none none We can calculate the
transconductances of Q1, Q2,
Q7 and Q8.
We can calculate the
transconductances of Q1, Q2,
and Q7.
245 6.1.1 6.1 6.3 none Av1 Av2
= -1043 V/V or 60.4dB
Av1 Av2
= 475 V/V or 53.5dB
248 6.1.2 6.3 none unnumbered ωz = 3.12mA/V / (5pF + 1pF) = 2π 82.8 MHz ωz = 3.12mA/V / 5pF = 2π 99.3 MHz
249 6.1.2 6.3 none unnumbered p2| = 3.12mA/V / 5pF = 2π 99.3 MHz ωp2 = 3.12mA/V / 1pF = 2π 497 MHz
250 6.1.3 6.4 none none … is only 0.05 V/s, … is only 0.05 V/μs,
254 6.2.1 none none none …introduce an additional approximately +20° phase shift… …introduce an additional approximately +20° to 30° phase shift…
258 6.2.2 6.7 none none the opamp and ωz, ωp, and ω2 are the frequencies
of a zero, the dominant pole, and the equivalent second pole, respectively.
the opamp and ωz, ωp1, and ω2 are the frequencies
of a zero, the dominant pole, and the equivalent second pole, respectively.
259 6.2.3 none none none Repeating equations (6.9) and (6.20) here, we have Repeating equations (6.42) with ß=1 and(6.20), we have
261 6.2.3 none none 6.71 lefthand side, denominator: Veff16 lefthand side, denominator: Veff9
268 6.4 none 6.19 none Dependent current source, Gmavi points down Dependent current source, Gmavi points up
279 6.5 none none none Third line: “The only difference them is…” The only difference between them is…
281 6.7 6.11 none none the unity-gain
frequency is increased by 150%
the unity-gain
frequency is increased by 100%
292 6.8 none 6.38 none Grounded nodes in the schematic These are AC grounds, and should be connected to a common-mode reference voltage
304 7.1.1 7.1(b) none none Vb = 1.1(450mV)+(200mV)/(0.9 √0.9) = 729mV Vb = 1.1(450mV)+(200mV)/(√0.9 √0.9) = 717mV
307 7.2.1 none 7.6 none Q13 size
is 100
Q13 size
is 25
309 7.2.1 none none none effective gate-source voltages increase by 27 percent effective gate-source voltages increase by 39 percent
309 7.2.2 none none none Q13 is five times greater … gate voltage of Q13 Q14 is five times greater … gate voltage of Q14
310 7.2.2 none 7.8 none Resistor label
“RB”
Resistor label should
use subscript: “RB
311 7.3.1 none none none Vbe will have approximately a -2mV/°K Vbe will have approximately a -2mV/K
313 7.3.1 7.4 none none For the special case
of T0 = 300°K
For the special case
of T0 = 300K
313 7.3.1 7.4 none none at 300°K at 300K
313 7.3.1 7.4 none none Recalling that 0°K Recalling that 0K
314 7.3.1 7.4 none 7.29 8 mV/°K / 1.24V = 6.5×10-6 parts/°K = 6.5ppm/K 8 mV/K / 1.24V = 6.5×10-6 parts/K = 6.5ppm/K
314 7.3.2 none none none the same collector currents and collector-emitter voltages the same collector currents and collector-base voltages
317 7.3.2 none 7.13(b) none opamp positive terminal on top opamp positive terminal on bottom
318 7.3.2 7.5 none 7.51 Now, recalling from
(7.26) that
Now, recalling from
(7.25) that
320 7.3.3 none 7.15 none Leftmost resistor is Ra Leftmost resistor is Ra/M
320 7.3.3 none 7.15 none Polarity of the opamp is incorrect with the positive terminal on the left Switch the polarity of the opamp so that positive terminal is on the right
325 7.4.3 7.6 none 7.74 RL/(rds1 + RL) -gm1R’L
326 7.4.3 7.6 7.21 none vgs,1 labeled incorrectly Should be labeled so that vgs,1 = v1 – vDD
326 7.4.3 7.6 7.21 none current source gm1 has wrong polarity reverse polarity of current source gm1
326 7.4.3 7.6 none 7.76 RL/(rds1 + RL) -gm1R’L
329 7.7.2 P7.7 none none Assume (W/L)12,13 = (2μm/0.2μm) and (W/L)12,13 = (8μm/0.2μm). Assume (W/L)14 = (2μm/0.2μm) and (W/L)15
= (8μm/0.2μm).
329 7.7.2 P7.10 none none an dc input a dc input
329 7.7.3 P7.12 and P7.13 none none 320°K 320K
330 7.7.4 P7.20(d) none none … so
that ωpL ≈ ωpa/100?
… so
that ωpL ≈ ωpa/10?
361 8.9.1 8.2 P8.2 none Vdd=5V Vcc=5V
361 8.9.1 8.9 P8.9 none Vdd=5V Vcc=5V
371 9.2.3 9.4 none none Kv2=(50nV2) Kv2=(50nV)2
378 9.3.1 none none none temperature (300°K) temperature (300K)
383 9.3.6 9.8 none none temperature of 300°K temperature of 300K
392 9.4.2 9.11 none none i.e. 300°K i.e. 300K
397 9.4.4 none none 9.122 2nd term, numerator: 4L2 16L2
400 9.5.2 none none none Δω = ω2 – ω Δω = ω2 – ω1
403 9.5.3 9.14 none none ID3 = 45 dB ID3 = -45 dB
408 9.8.2 P9.11 and P9.12 P9.11 and P9.12 none y-axis title: Vrms y-axis title: Vrms2
420 10.3 10.3 none none VDD = 1V VDD = 2V
420 10.3 10.3 none none -2.8mV charge injection; total of -56mV -28mV charge injection; total of 80mV
467 11.9.3 P11.11 none none Equation
denominator: “Chld + Cbe6
Equation
denominator: “Chld + Cbe6
+ CF
471 12.1.2 none none none independent of the feed-in gain, K1,2,3. independent of the feed-in gain, K0,1,2.
471 12.1.2 none none none determined by the feed-in gain, K1,2,3. determined by the feed-in gain, K0,1,2.
472 12.1.2 12.1 12.3 none 1/Q = √2 1/Q = -√2
477 12.2.4 none none 12.26 s(Gm3 / Cx+ Cb) s(Gm3 / Cx +CB)
478 12.2.4 none none 12.31 Gm3 / Cx+ Cb Gm3 / Cx +CB
482 12.3 12.5 none none For the case re,max < 0.01Re For the case re,max < 0.01Rs
482 12.3 none 12.13 none Gm = 1/Re Gm= 1/Rs
482 12.3 none 12.14 none Gm = 1/Re Gm = 1/Rs
492 12.4 none none 12.90 Gm = μnCox(W/L)1VDS Gm = (1/2)μnCox(W/L)1VDS
492 12.4 12.7 none none Gm = 96 μA/V2 x 10 x 0.2 V = 0.192 mA/V Gm = (1/2) x 96 μA/V2 x 10 x 0.2 V = 96 μA/V
510 12.8.1 12.10 12.41(b) none Vno Vpo
510 12.8.1 12.10 12.41(b) none Vpo Vno
536 12.13.4 P12.20 none none Sketch the resulting
magnitude response |Vin(ω)/Vout(ω)| …
Sketch the resulting
magnitude response |Vout(ω)/Vin(ω)| …
554 13.6 13.8 none none at 40kHz and 60kHz
is 0.2399 and 0.1559,
at 40kHz and 60kHz
is 0.2339T and 0.1559T,
568 14.2.3 none 14.13(a) none vco(nT-T) vco(nT-T/2)
568 14.2.3 none 14.13(b) none vci(nT-T/2) and vco(nT-T/2) vci(nT) and vco(nT)
571 14.3 none none none … a rms voltage Vc12(rms)= √kT/C … … a rms voltage Vc1 (rms)= √kT/C …
571 14.3 none none none … capacitor noise
voltage Vc22(rms)= √kT/C.
… capacitor noise
voltage Vc2(rms)= √kT/C.
573 14.4 14.3 none none the bilinear
transform p = (z-1) / (z+1)
the bilinear
transform s = (z-1) / (z+1)
574 14.4 none none none As in Example 14.2, As in Example 14.3,
577 14.4.2 none 14.21 none Φ1, Φ2 swap clock phases near C3: Φ2, Φ1
605 14.12.6 P14.20 none none ensure a dc offset
of less than 5mV
ensure a output dc
offset of less than 5mV
605 14.12.6 P14.21 none none Find the resulting
dc offset
Find the resulting
output dc offset
619 15.5.3 15.4 none none For the gain error,
from (15.25) we have
For the gain error,
from (15.24) we have
627 16.1.2 none 16.4 none   The LSB decoder at the bottom of the figure must also accept as input the digital signal b2 since the folded resistor-string changes direction.
642 16.5 none none none … employ an array of
2N-1 unitary …
… employ an array of
2N-1 unitary …
669 17.4.1 17.7 none none V3 = 2(V2-Vref/4)
= -540V
V3 = 2(V2-Vref/4)
= -540mV
669 17.4.1 17.7 none none Vin =
375mV
Vin =
312.5mV
669 17.4.2 none none 17.42 Vin = Vref/2 (S(bi,0 + bi,1 – 1)2-i + bn-1,12N-2
+bN-1,02N-1)
Vin = Vref/2 (S(bi,0 +bi,1 – 1)2-i + bn-1,12-N+2
+bN-1,02-N+1)
670 17.4.2 none none none 0,1| < Vref/4 0,1| < Vref/8
671 17.4.2 17.8 none none V2 = 2(V1
– V1x) = -200mV
V2 = 2(V1
– V1,x) = -200mV
671 17.4.2 17.8 none none   left-align the variables “b1,0“,
“b1,1“, and “b2,1 b2,0
in the table
681 17.7 none 17.31 none The bottom of the resistor string is grounded. The bottom of the resistor string should be connected to an additional amplifier output that compares the input, Vin, to ground.
693 17.12.5 P17.22 none none the reference voltage supply Vref. the reference voltage supply Vref
= 0.5V.
708 18.2.4 none none none Key Point: … 1.5 bits/octave 2.5 bits/octave
711 18.3.1 none none none f0 = 44.1 kHz 2f0 = 44.1 kHz
711 18.3.1 none none none end of first paragraph: … often an desirable trade-off … … often a desirable trade-off …
720 18.5.2 none none 18.44 RHS of 1st line: ŜTF2(z)X1(z) + N̂TF1(z)X2(z) ŜTF2(z)X1(z) – N̂TF1(z)X2(z)
720 18.5.2 none none 18.44 RHS of 2nd line: all terms are positive RHS of 2nd line: 3rd and 4th terms (those including N̂TF1) should be negative
720 18.5.2 none none 18.45 RHS: ŜTF2(z)STF1(z)E1(z) + N̂TF1(z)NTF2(z)E2(z) ŜTF2(z)STF1(z)E1(z) – N̂TF1(z)NTF2(z)E2(z)
722 18.6 none 18.23 none Modulator as drawn
is unstable
Modify H(z) so that z-2 appears in the feedback loop and there
is no delay in the feedforward path.
729 18.8.4 none none 18.55 first term on the right-hand-side of the equals sign: U(z)z-1 U(z)z-1/(2-z-1)
729 18.8.4 none none 18.55 exponent in
the 3rd and 4th terms on the right-hand side: (1-z-1)-2
(1-z-1)2
730 18.8.4 none 18.29 none Gain “1/2”
appears between 2nd and 3rd summers at the top left of the figure
To make it consistent with the reference [Hairapetian, 1994], the gain “1/2” should be moved to between 1st and 2nd summers at the top left of the figure
730 18.8.4 none 18.29 none box at lower-right
hand corner, with Us(z) as its input, contradicts the reference [Hairapetian, 1994]: 2(1-z-1)2
2-z-1
732 18.10 none none none second Key Point: LSB2/12 LSB2/12
742 19.1.3 19.1 19.3 and 19.4 none waveform labels: Vosc waveform labels: Vdiv
746 19.1.4 none none none section title: Loop Filer Loop Filter
750 19.2.1 none 19.9 none caption: “(a) time-domain step response; (b) frequency domain jitter transfer function magnitude response” caption: “(a) frequency domain jitter transfer function magnitude response; (b) time-domain step response”
760 19.3 19.11 none none 1st and 3rd
equations, second bracketed term includes “gm
1st and 3rd
equations, second bracketed term, “gm1
760 19.3 19.11 none none 2nd equation, right-hand
side: “nk / |Vs|”
2nd equation, RHS:
“nk / |Vs|
gm (Rd||ro1)”
760 19.3 19.11 none none 3rd equation, term
preceding the brackets: “(Rd||ro1)2 /
|Vs|2
3rd equation, term
preceding the brackets: “1 / gm2 |Vs|2
764 19.3.5 19.15 none not numbered Denominator of the exponent: 5·10-25 5·10-23
778 19.5.2 19.19 none 19.95 denominator is
incorrect
778 19.5.2 19.19 none 19.96 denominator: “2ωpll denominator: “4ωpll
784 19.8.3 P19.14 none none zero crossing times: “… 40.2ns, 41.0ns, 49.0 ns,
…”
zero crossing times: “… 40.2ns, 49.0 ns, …”
End papers none none none none g = 2ID / Veff gm = 2ID / Veff
End papers none none none none Endpaper CMOS technology
parameter values differ slightly from those in Table 1.5.
Posted problem solutions use the values in Table
1.5.

97 thoughts on “Analog IC Design Errata”

  1. Sect. 9.4.4, page 397, equation 9.122:
    I believe the algebra is such that the second term should be 16/9, not 4/9, after setting Cgs = Cin from equ. 9.121.

    Thanks, great book.

    Reply
  2. Pg. 190, Eq. 4.203, Sec. 4.4

    Shouldn’t we have Gin(Cgs1 + Cs) instead of Gin(Cs) in denominator for expression for Q?

    Thank you in advance.

    Reply
  3. on page 244, equation 6.1 says:

    Av1 = -gm1(rds2||d*rds4)

    where it should just say:

    Av1 = -gm1(rds2||rds4)

    In other words, there’s a minor typo which adds in a ‘d’ next to rds4 that should not be there.

    Reply
  4. There is one sentence in page 130 which does not make sense. Whoever was the author of this sentence is grossly incompetent in English. There are many many other mistakes but this mistake is very severe since this disrupts understanding of a very important part

    “Since the smallest output voltage,VD4
    , can be without Q4 entering the triode region is given by Vds2+Veff , the minimum allowed voltage for Vout is give by”

    Reply
    • Thanks for catching this. It should read, “…Since the smallest the output voltage, VD4, can be…” This now appears in the errata above. We’d be happy to hear about the other mistakes you’ve noticed.

      Reply
  5. figure 1.30(a) on page 46 (second edition): the current Id seems unusually large versus Vgs… should the unit for Id be mA rather than A? If using this plot, by plugging in theta = 1.7V^-1, Vgs = 1V, Id = 0.3A, Vth = 0.45V (gives muCox(W/L)=2.72mA/V^2), one will get m = -0.106 by using equation 1.126. But if changing Id = 0.3A->0.3mA, one will arrive m = 2 that is more reasonable.

    Reply
  6. hi there,

    (4.175) is Cout=Cgd2+Cdb2+CL+Cbias=20pF+25fF+7pF+25pF=52.025pF

    (4.175) should be Cout=Cgd2+Cdb2+CL+Cbias=20fF+25fF+7pF+25pF=32.045pF

    br,

    mario

    Reply
    • I believe you are using some of the wrong values. The sum is Cout = 15fF + 20fF + 5pF + 20fF = 5.055 pF, which is the correct value given in equation (4.175).

      Reply
  7. Dear professor,

    About the problem 10.4 on page 442. The problem can be solved and that is clear for me. However, if the input signal Vin can be only positive value because supply voltages are gnd and 5V so can the comparator output go to high? So do we have the think that the input Vin is just relative signal like positive or negative?

    Best regards,

    Jan

    Reply
  8. Page 111 and Fig. 2.36
    Why not connecting the metal shield to VDD?
    Last three lines in 2nd paragraph mention that the nwell acts as a bypass cap. This is true if the shield is VDD rather than GND.
    Also in this sentence VDD should probably be replaced by GND: “this helps minimize noise in the substrate, which is connected to VDD”

    Reply
    • Yes, this paragraph is jumping around, mixing up a few different possibilities. The intention is to connect such shields to a dc voltage via a very low impedance (i.e. a small-signal ground). This may be either VDD or ground. Generally, ground has the lowest impedance. Moreover, if a dedicated shielding ground is used, as suggested in the text, it should have less noise on it. However, if VDD is used, you may get the benefit of additional bypass capacitance. Finally, of course, a p-type substrate as pictured in Figure 2.36 would normally be connected to ground, as you said. Thanks for your comment!

      Reply
  9. I have one question about a circuit proposed several times in the book in Fig. 14.34, Fig. 14.35, Fig. 14.36, and Fig. 16.12. In this circuit there is no DC path for the inverting terminal of the op-amp. This node is always floating, and it is not set by any of the switches. I would appreciate if you can let me know how you set the DC bias at this point.

    Reply
    • Capacitor C3 in Fig. 14.34 is alternately switched between ground and the inverting input terminal of the op amp. Over several clock cycles, this provides a path for charge to flow to or from the inverting input terminal, allowing its voltage to settle to an appropriate value.

      Reply
  10. chapter 7, fig15. (Banba Bandgap reference)

    to make valid eq(7.57)
    resistor Ra in the right side should be Ra/M
    and I2a_right = I2a_left/M.

    Reply
  11. Section 18.3.1 (p.710) specifies fs=5.6448 MHz and f0=44.1 kHz to give an OSR=128. But per the definition of OSR used in the book (eq. 18.8), this should give an OSR=fs/(2*f0)=64. I assume the intention here might be to say 2*f0=44.1 kHz ?

    Reply
  12. Hi, in eqn 6.43, zero is on the left-half plane if Rc=0. It has to be on the RHP. Actually, if you look at the sentence below also, it mentions that if Rc is too large, zero will move from RHP to LHP. It think there is an extra (-) sign in that eqn.

    Reply
    • No. The convention used throughout that section of the book, and in most analog circuit analysis, is that when a pole (or zero) frequency is positive, it refers to a left-half plane pole (or zero). See, for example, equations (6.19), (6.20), and (6.21) all of which are positive describing left-half plane poles and zeros. Thus, the negative value of (6.43) when Rc=0 implies a right-half plane zero, as expected.

      Reply
  13. There is an error in the errata. For the correction of the mistake in page 320 regarding opamp polarity, it is mentioned that the ref figure is “none”. The ref figure is Fig. 7.15. Please correct.

    Reply
  14. Page 314, Section 7.3.2:
    “both transistors have the same collector currents and collector-emitter voltages”
    Should be “and collector-base voltages”.

    Reply
  15. Section 7.2.1, page 309, 2nd paragraph:
    1) The reduction in mobility is 28%, not 27%.
    2) If the mobility decreases by 28%, then Veff should be: Veff/0.72 = 1.39Veff –> Veff should increase by 39%, not 27%.

    Reply
  16. Example 7.1-b)
    ID is in inverse proportion to R.
    BUT Veff is proportional to sqrt of ID rather than ID.
    Thus, “0.9” should be replaced by “sqrt(0.9)”.
    The correct answer should be 717mV

    Reply
    • Right. The current density of Q14 is five times greater than that of Q4. Hence, the gate voltage of Q14 is suitable for use as the PMOS cascode bias Vcasc-p. Added to the errata – thank you!

      Reply
  17. page 420,Example 10.3, solution part:second line,”using (10.8),this …=-2.8mV”,i think it is “-28mV”,dose it mean: 2Vx1.4fF/101.4fF=2.8mV ?

    Reply
    • Yes – you are correct. The charge injection due to overlap capacitance should be 27.6mV and so the total charge is found by adding 27.6mV and 52.7mV for a total of 80mV. I have added this to the errata.

      Reply
  18. On page 24(second ed.), you state that for a p-channel MOS to conduct, it must have VSG>Vtp, where Vtp is a negative quantity. So as a consequence, VSG=0 gives a conducting transistor since 0 is greater than any negative number, but this cannot be true ??

    Reply
    • It is easy to get the signs confused in this context. Without having to get into the weeds of it myself, it is clear that your understanding of the matter is correct!

      Reply
    • I don’t see why this hasn’t been added to the errata. It is an obvious mistake and it seems silly to have to find it in the comments.

      Reply
      • This is not included in the errata because, strictly speaking, the text is correct. For example, consider equation replacing VGS with VSG and Vtn> with -Vtp, as indicated in the text. The final term of (1.63) becomes (VSG + Vtp). Since Vtp is a negative quantity and the square law is only valid when the bracketed term is greater than zero, we must have VSG > |Vtp| for the transistor to be “on” with current flowing, as we expect.

        However, I understand that all these minus signs can be confusing and I just wanted to assure Anders that I believe his basic understanding is correct.

        Reply
  19. Dear Professors,

    The equations 5.2 and 5.3 in Chapter 5 should have a negative sign for the loop-gain term. If we set input to zero for loop-gain calculations, and follow the loop in Fig.5.1, v=-ABx and L=-AB, due to terminal v multiplying with -1. This also implies that there is a negative feedback. These equations should be included in the list of errata.

    This book is one of my favorites and I liked this time in 2nd edition, topic of feedback was given more attention.

    Thanks

    Reply
    • The book adopts the more common convention of defining the loop gain of a negative feedback amplifier as positive (at low frequency). The signal x experiences gains of A and then B to the point V so the gain from X to V is AB not -AB. If one defines L=-AB, then all the equations of 5.4 and onward must also be modified.
      V=ABX=AB(U-V) so V=U.AB/(1+AB) & Y=A(U-V) so Y=U.A/(1+AB)

      Reply
  20. In the solution of Example 5.1 on page 206 the change in the closed-loop gain should be less than 5%, because |4.9751-4.9975|=0.0224, which is 2.24% change.

    Reply
  21. I believe 4.133 is incorrect. It should be
    wp2 = 1/(RS*(Cgs1+Cgd1))

    4.133 is derived assuming C2 is large directly on 4.127,
    However we cannot not use 4.127 directly (4.127 is based on the assumption that Cdg1*gm1*R2 >> R2*C2 which is in contradiction with the case we are considering in 4.132.

    Reply
    • There is no contradiction in the most common cases.

      The assumption of widely-spaced real poles which leads to (4.126) & (4.127) is tantamount to assuming the Miller capacitance, Cgd1*gm1*R2 >> C2. This is reasonable in the common case where Cgd1 includes a compensation capacitor Cc so that the Miller effect makes it much larger than C2.

      Then, in order to arrive at (4.133) from (4.127), we assume C2 >> Cgs1, also reasonable assuming the opamp is loaded by a capacitance much bigger than Cgs1. This then allows us to neglect the term Cgs1*Cgd1 in the denominator of (4.128) as being much smaller than C2*Cgd1.

      Reply
    • Yes – you are correct. Example 1.13 should more properly refer to Cov‘, the overlap capacitance normalized per unit length of gate width. Hence, Cov = Cov‘ W. Thanks for catching this!

      Reply
  22. In EXAMPLE 1.16,I have a question about the definition of Ioff. Only when VGS=0,we have Ioff. Then Ioff has nothing to do with the changes of VGS,and it is a function of vth. Is that Right,Dr Carusone?

    Reply
    • Yes – your interpretation is consistent with equation (1.121). This definition is particularly suitable for CMOS digital logic circuits where the MOSFETs act as switches that are OFF when VGS = 0. In analog circuits, sometimes the source (and even the body terminal) may not be at ground. It may be possible to reduce subthreshold leakage in these cases by decreasing VGS even further, below zero. Thanks for raising this confusing point!

      Reply
  23. The second pole and zero frequency is incorrect in example 4.7 on page 159-163. The circuit shows 1pF, but the calculations must have used 100pF, because the frequency is off by 100.

    Reply
  24. On page 182,Equation4.168 Rout is rds2//RL.I think Rout is gm2rds2rds1//RL;
    Equation4.170,gs2=1/rs2=gin2+gds1,gin2 I think is gm2;
    Equation4.171 I think gin2 is gm2 too.

    Reply
    • Equation (4.168) refers to rd2 which is the small-signal resistance seen looking into the drain of Q2, not simply rds2 as you suggest. The substitution for rd2 is then made in (4.174). In equations (4.170) and (4.171), note that gin2 is approximately gm2, but is more accurately given by the expression in (4.160) which takes into account the circuit’s finite load impedance.

      Reply
  25. Page 124, last paragraph, first sentence:
    “…, the input impedance, rout, is found to be 1/gm…” -> rout should be rin.

    Reply
    • No, not quite, although of course there is a typo there. In fact, in equation (6.71) Veff16 should be replaced by Veff9, the triode device realizing Rc. Thanks.

      Reply
  26. Page 196 Fig. 4.35 right-hand side dependent current source arrow should be upwards since vgs2=-vg1/2. Then page 195 Eqn. 4.226 becomes positive.

    Reply
    • Yes – for Fig. 7.13(b) only they should be reversed in order to provide negative feedback, and in accordance with Ye’s paper. Fig. 7.13(a) is correct as is. Thanks!

      Reply
  27. Page 510, Ex. 12.10, Fig. 12.41(b): Output differential voltage polarization should be reversed in order to have a negative gain of (-1/(sRC)) as stated in the solution.

    Reply
  28. Page 225 example 4.9 solution:
    Fig. 5.13b: simplified small-signal model of the diff pair’s dependent current source direction should be reversed (Av=+gm*Rout).
    Then Fig. 5.13c becomes correct for dependent current source:
    gm1(Vin-Vout)”up arrow”
    = gm1(0-Vt) “up arrow”
    =-gm1*Vt “up arrow”
    = gm1*Vt “down arrow”

    Reply
  29. Page 170 example 4.8 solution:

    In the first sentence, Miller feedback admittance is stated as “Y(s)=1/sC”,which should be Y(s)=sC.

    Reply
  30. on page 446 says Since this charge is negative, it will cause the junction voltages to have negative glitches.
    i think positive charge is right since switch of Fig.11.3 is PMOS transistor.

    Reply
  31. In p.145 sec. 4.1 last sentence in last paragraph.
    “Further, the real parts of all the poles will be positive for stable transfer functions.”
    The term “positive” should be modified as “negative”!

    Reply
    • The H(s) in the Ex. 4.3 is a high-pass filter, sRC/(1+sRC). Which part of the example shows a low-pass transfer function? I got a little confused by this. The basic formula looks like low-pass, but as the circuit transfer function derives, it is clear a high-pass filter, doesn’t it? Thank you.

      Reply
      • The capacitor acts like open circuit at DC and short circuit to ground at very high frequencies. So the circuit will pass the DC content and the capacitor will attenuate the signal at very high frequencies. This result can also be confirmed with mathematical transfer function of the circuit:
        The transfer function is just a voltage divider between the capacitor and the resistor impedances:
        H(s) = (1/Cs) / (R+1/Cs) = 1/(1+RCs)
        which is a lowpass transfer function. (If you replace s=0 for DC: H=1; and if you replace s=infinity: H=0)

        Reply

Leave a Reply to Prof. Tony Cancel reply